A request-based gate clock generation circuit (CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK)

摘要

A request-based clock circuit generates a gate clock signal based on the request. The latch circuit data input receives an enable signal. The clock input receives a first periodic input clock signal. The latch circuit data output provides a shifted enable signal which is the first input signal from the first logic state to the second logic state of the first input clock signal after the enable signal transitions from the inactive logic state to the active logic state, Transition from an inactive logic state to an active logic state at the time of transition. The logic circuit provides a gate clock signal which is the first transition from the second logic state of the second input clock signal to the second logic state after the shifted enable signal transitions from the inactive logic state to the active logic state Such that the gate clock signal transitions from the active logic state to the inactive logic state and transitions from the active logic state to the inactive logic state upon transition of the enable signal shifted from the active logic state to the inactive logic state.