testing of import and ausgangsstufen in integrated circuits

摘要

Digital integrated circuit testable input/output pad logic includes modified output driver logic (66,86) and a latch (54,55) for storing a test bit provided externally at the I/O pad terminal (10). The output driver logic selects either the normal pad output signal (O) for output during normal operation, or the stored test bit (S) or its complement (S min ) for output during a test operation. The output driver logic and latch are controlled by control logic signals (DP,SP,NDN,LS,NLS,NSN) derived from common tri-state (NTR) and latch (NTM) test signals provided externally at dedicated test pins (NTR,NTM). The control logic signals are provided over a bus (50) to all similar testable I/O pads for testing all testable I/O pads within the IC under control of the two test signals. IMAGE IMAGE