Testing integrated circuit designs on a computer simulation using modified serialized scan patterns

摘要

A method to test an integrated circuit design on a computer simulation loads a desired simulation test vector in parallel into a scan chain (30). The simulation loads the desired vector at a slight offset or upstream shift allowing several serial shifts of the loaded vector through the scan chain (32). After the serial shifts, the initial IC state is set for executing an IC function (34). The IC function includes applying an input on the external pins and receiving an output from the external pins, given the initial IC state loaded by the simulation. After executing the IC function, the simulation unloads the resulting IC state in parallel (36) and compares the resulting IC state to a target vector (38).