In-phase signal output circuit, opposite-phase signal output circuit, and two-phase signal output circuit

摘要

In an output circuit, a signal /&phgr; opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal &phgr; in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /&phgr; changes at an output terminal 4) to another delay time (to when the level of the signal &phgr; changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/&phgr; and . phi. at two output terminals 4 and 5.