Memory control unit with programmable edge generator to minimize delay periods for critical DRAM timing parameters

摘要

A system is disclosed for minimizing delays for critical timing parameters during DRAM transactions. The present invention comprises a modified memory control unit which includes a programmable DRAM edge generator for increasing the resolution times for assertion of DRAM control signals that operates using both edges of the memory clock. The memory control unit (or MCU) includes configuration registers that are configured during system initialization by the BIOS to set desired delay times for critical DRAM timing parameters, such as assertion of the row address strobe (RAS) signal, the assertion of the column address strobe (CAS) signal, and the timing of the switch from the row address to the column address. The DRAM edge generator includes shifter delay circuits that control the timing of the control signals based upon the status of the configuration registers. The shifter delay circuits also receives an enable signal from the DRAM controller, a precharge signal from a bank precharge counter, and bank and byte select signals from the DRAM address router.