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Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

机译：通过了解和利用DRAM时序参数边缘来提高DRAM性能，安全性和可靠性

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作者
Kim, Jeremie S.;
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作者单位

Carnegie Mellon University.;

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授予单位 Carnegie Mellon University.;
学科
学位 Ph.D.
年度 2020
页码 199 p.
总页数 199
原文格式 PDF
正文语种 eng
中图分类 AAI28091904;
关键词
Computer Architecture; Computer Systems; DRAM; Performance; Reliability; Security;

机译：计算机架构;计算机系统;DRAM;表现;可靠性;安全;
入库时间 2022-08-17 12:02:12

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1. Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM [J] . Lv Minjie, Sun Hongbin, Ren Qiwei, Circuits and Systems I: Regular Papers, IEEE Transactions on . 2015,第5期

机译：Logic-DRAM协同设计可利用堆叠式DRAM的高效修复技术
2. Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems [J] . Yuhwan Ro, Minchul Sung, Yongjun Park, IEICE Electronics Express . 2017,第11期

机译：选择性DRAM高速缓存绕过，可提高DRAM / NVM混合主存储系统的带宽
3. L-Shaped Tunnel Field-Effect Transistor-Based 1T DRAM With Improved Read Current Ratio, Retention Time, and Sense Margin [J] . Kamal Neha, Kamal Alok Kumar, Singh Jawar IEEE Transactions on Electron Devices . 2021,第6期

机译：L形隧道场效应晶体管的1T DRAM，具有改善的读取电流比，保留时间和感测边距
4. Exploiting expendable process-margins in DRAMs for run-time performance optimization [C] . Chandrasekar, Karthik, Goossens, Sven, Weis, Christian, Design, Automation & Test in Europe Conference and Exhibition . 2014

机译：利用DRAM中的消耗性工艺裕量进行运行时性能优化
5. Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service. [D] . Tran, Le-Nguyen. 2013

机译：DRAM / eDRAM和3D-DRAM的省电方法，利用工艺变化，温度变化，设备降级和内存访问工作负载变化，以及使用具有服务质量的3D-DRAM的创新的异构存储管理方法。
6. Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM [O] . Hyeonjeong Kim, Songyi Yoo, In-Man Kang, 2020

机译：硅和多晶硅1T-DRAM的传感裕度分析
7. Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case [O] . Lee, Donghyuk, Kim, Yoongu, Pekhimenko, Gennady, 2015

机译：自适应延迟DRAM：针对常见情况优化DRAM时序

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

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