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Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate
Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate
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机译:在半导体衬底内形成互补的n型掺杂和p型掺杂有源区的半导体处理方法
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摘要
A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate; c) providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region; d) patterning the insulating layer to provide a void therethrough to the desired first conductivity type region; e) filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1×10. sup.20 ions/cm.sup.3, the desired first conductivity type region having a first conductivity type dopant concentration prior to the filling step which is in the range of from 0 ions/cm.sup.3 to 1×10.sup.19 ions/cm.sup.3 ; and f) annealing the substrate for a period of time effective to out-diffuse first conductivity type dopant impurity from the first conductivity type doped polysilicon plug into the substrate to form the desired first conductivity type active region having a first conductivity type dopant impurity concentration of at least 1×10. sup.20 ions/cm.sup.3 in the substrate. Methods of forming CMOS FET transistors, and SRAM and DRAM CMOS circuitry are also disclosed.
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机译:一种在半导体衬底内形成互补的第一导电类型掺杂的有源区和第二导电类型掺杂的有源区的半导体处理方法,包括:a)提供半导体衬底; b)掩蔽衬底的期望的第一导电类型区域,同时将第二导电类型掺杂进行到衬底的期望的第二导电类型有源区域中; c)在所需的第一导电类型区域和第二导电类型掺杂区域上方的衬底上提供绝缘层; d)对绝缘层进行构图以提供穿过其中的空隙到所需的第一导电类型区域; e)用第一导电类型掺杂的多晶硅塞填充所述空隙,所述塞具有至少1×10的第一导电类型掺杂剂杂质浓度。参见20离子/ cm 3,在填充步骤之前具有第一导电类型掺杂剂浓度的期望的第一导电类型区域在0离子/ cm 3至1×10 s的范围内。 .19离子/cm.3; f)将衬底退火一段时间,以有效地将第一导电类型的掺杂杂质从第一导电类型的掺杂的多晶硅塞扩散到衬底中,以形成期望的第一导电类型的有源区域,该有源区域的第一导电类型的掺杂杂质的浓度为至少1×10。基材中的最大20离子/ cm 3还公开了形成CMOS FET晶体管的方法以及SRAM和DRAM CMOS电路。
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