首页> 外国专利> Method of designing mask pattern or direct depicting pattern on a wafer for forming a semiconductor integrated circuit and design rule confirmation method

Method of designing mask pattern or direct depicting pattern on a wafer for forming a semiconductor integrated circuit and design rule confirmation method

机译:在用于形成半导体集成电路的晶片上设计掩模图案或直接描绘图案的方法和设计规则确认方法

摘要

A method for designing mask patterns or direct depicting patterns using CAD for forming a semiconductor integrated circuit including a plurality of laminated semiconductor layers includes inputting design rules for performing a design rule check (DRC) of n patterns, where n is an integer larger than 2, n mask layers, or n direct depicting patterns for forming n semiconductor layers; editing the input design rules into matrix notation; designing patterns for the n mask layers or n respective semiconductor layers; displaying the designed patterns on a CRT; performing a DRC of the patterns using the design rules edited into the matrix notation; modifying the checked patterns to satisfy the design rules edited into the matrix notation; and outputting the design rules and the modified patterns. The efficiency of the confirmation and setting of the design rules can be enhanced, reducing design mistakes.
机译:一种用于使用CAD设计掩模图案或直接描绘图案以形成包括多个层叠的半导体层的半导体集成电路的方法,该方法包括输入用于执行n个图案的设计规则检查(DRC)的设计规则,其中n是大于2的整数,n个掩模层或n个直接描绘的图案,用于形成n个半导体层;将输入设计规则编辑为矩阵符号;为n个掩模层或n个相应的半导体层设计图案;在CRT上显示设计的图案;使用编辑为矩阵符号的设计规则对图案进行DRC;修改检查的图案以满足编辑为矩阵符号的设计规则;并输出设计规则和修改后的图案。可以提高设计规则的确认和设置效率,减少设计错误。

著录项

  • 公开/公告号US5681674A

    专利类型

  • 公开/公告日1997-10-28

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI KABUSHIKI KAISHA;

    申请/专利号US19960589293

  • 发明设计人 SHINICHI FUJIMOTO;

    申请日1996-01-22

  • 分类号G03F9/00;

  • 国家 US

  • 入库时间 2022-08-22 03:09:11

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