EPLD CHIP WITH HYBRID ARCHITECTURE OPTIMIZED FOR BOTH SPEED AND FLEXIBILITY.

摘要

A hybrid EPLD architecture has multiple first blocks (FB2-FB11) each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple second blocks (FFB0-FFB1) each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix (UIM) for interconnecting all the blocks.