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Arithmetic circuit for calculating a square-root of a sum of squares
Arithmetic circuit for calculating a square-root of a sum of squares
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机译:用于计算平方和的平方根的算术电路
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摘要
The present invention is intended to provide an arithmetic circuit composed of a small number of parts, which can perform high-speed arithmetic operations for calculating a square-root of a sum of squares of two numbers. An arithmetic circuit according to the present invention provides absolute values of two inputs Sin1 and Sin2 are determined by absolute value calculators (1 and 2) respectively and are compared with each other by an absolute value comparator (3). According to the comparison result, a multiplexer (4) selects the smaller of the two absolute values and a multiplexer (5) selects the larger of the two absolute values. The smaller absolute value is shifted by a 2-bit right shifter (6) and by a 3-bit right shifter (7) respectively and the obtained results are added together by a (N-2)-bit adder (8). The sum of the shifted values is then added by a N-bit adder (9) to the larger absolute value. A square-root of the square-sum of two inputs Sin1 and Sin2 is thus approximately determined.
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