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arithmetic circuit for calculating square root of sum of squares

机译:计算平方和的平方根的算术电路

摘要

The present invention is intended to provide an arithmetic circuit composed of a small number of parts, which can perform high-speed arithmetic operations for calculating a square-root of a sum of squares of two numbers. An arithmetic circuit according to the present invention provides absolute values of two inputs Sin1 and Sin2 are determined by absolute value calculators (1 and 2) respectively and are compared with each other by an absolute value comparator (3). According to the comparison result, a multiplexer (4) selects the smaller of the two absolute values and a multiplexer (5) selects the larger of the two absolute values. The smaller absolute value is shifted by a 2-bit right shifter (6) and by a 3-bit right shifter (7) respectively and the obtained results are added together by a (N-2)-bit adder (8). The sum of the shifted values is then added by a N-bit adder (9) to the larger absolute value. A square-root of the square-sum of two inputs Sin1 and Sin2 is thus approximately determined. IMAGE
机译:本发明旨在提供一种由少量部件组成的算术电路,其可以执行用于计算两个数的平方和的平方根的高速算术运算。根据本发明的算术电路提供两个输入Sin1和Sin2的绝对值,分别由绝对值计算器(1和2)确定,并且由绝对值比较器(3)相互比较。根据比较结果,多路复用器(4)选择两个绝对值中的较小者,而多路复用器(5)选择两个绝对值中的较大者。较小的绝对值分别由2位右移器(6)和3位右移器(7)进行移位,并且所获得的结果由(N-2)位加法器(8)相加。然后,由N位加法器(9)将移位后的值的总和与较大的绝对值相加。因此,近似确定两个输入Sin1和Sin2的平方和的平方根。 <图像>

著录项

  • 公开/公告号DE69715309D1

    专利类型

  • 公开/公告日2002-10-17

    原文格式PDF

  • 申请/专利权人 SHARP K.K. OSAKA;

    申请/专利号DE19976015309T

  • 发明设计人 ONODERA TAKASHI;

    申请日1997-06-05

  • 分类号G06F7/552;

  • 国家 DE

  • 入库时间 2022-08-22 00:24:55

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