How to implement synchronous dynamic random access memory device and programmable cache storage policy in cache

摘要

A cache-embedded SDRAM device having a multi-bank architecture of the present invention includes a row decoder connected to a memory bank array for selecting a data row in a memory bank array, Sense amplifiers coupled to the memory bank array for latching data rows selected by the row decoder and synchronous column select means for selecting desired columns of the data row do. A randomly addressable row register stores the data row latched by the sense amplifier. A select logic gate means disposed between the sense amplifier and the row register selectively gate the data row provided on the bit line to the row register according to the performance of a particular synchronous memory operation of the cache embedded SDRAM. During the write operation, data input to the cache-embedded SDRAM is received by the sense amplifier and written to the memory bank array. During the read command, the data output from the cache-embedded SDRAM is read only in the row register, and the data row contained in the row register is first read from the memory bank array to the sense amplifier and then selectively read into the row register according to the operation of the specific synchronous memory Gated.