High Speed Multiplier with Pipeline Stage

摘要

The present invention relates to a high speed multiplier using a pipeline stage, in particular a first register for inputting first input data input through a data line; A second register configured to receive second input data input through the data line; Multiplication means for complementing and outputting the output values of said first and second registers; Pipeline stage means for generating a final result of the multiplication operation output from said multiplication means in synchronization with a system clock; And a third output register for storing a value output from the pipeline stage means.;Accordingly, the present invention is effective in providing a high speed multiplier using a pipeline stage for speeding up the speed of the multiplier according to the increase of the system clock speed.