A VHDL based methodology for the automatic pipelining of floating-point multipliers.

摘要

Automated synthesis tools are now an integral part of the EDA design cycle, allowing the hardware engineer to describe a function using a hardware description language such as VHDL, and letting the synthesis tool generate an optimized netlist. There are certain limitations to the optimization capabilities of synthesis tools, for example, an addition operation can be described by one line of VHDL code, but when the code is synthesized and optimized the contents of the final netlist will totally depend on the synthesis tool; the engineer has lost control of his design. The only way to control this is to generate a more detailed description of the design, which reduces the advantages of using a HDL.;The lack of design control has serious implications for both speed and area of the final layout, decreasing the ability to optimize the design past the synthesis tool's capabilities without some manual intervention. A floating point multiplier, described in VHDL for use in a real-time system, could be synthesized and optimized for speed and/or area, but the final netlist may still not meet the required performance criteria, within the parameters of the VHDL description. A solution to this problem is to use pipelining to increase the throughput of the multiplier. Automated synthesis tools currently do not have the ability to analyze a circuit and modify the VHDL code to contain pipeline stages, therefore the designer is required to manually redesign the circuit (or the high level description) to include pipeline registers.;This thesis describes a methodology to automate the design and synthesis of an n-bit pipelined floating-point multiplier, described in VHDL. This methodology has been implemented in a single program, which performs the VHDL compilation as well as the delay analysis of the netlist synthesized from the VHDL.