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Parity test circuit for memory with twice the speed display valid
Parity test circuit for memory with twice the speed display valid
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机译:具有两倍速度显示的存储器奇偶校验测试电路有效
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摘要
A memory which is cleared by simultaneously clearing a special bit in each entry within the memory, an extra bit, used for other purposes, is also cleared. When both bits have a value of 0, parity checking is disabled. When either bit has a value of 1, parity checking is enabled. This prevents incorrect detection of parity errors after the memory device has been cleared. IMAGE
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