首页> 外国专利> Error correction circuit for dynamic RAM system, has read tree to receive data from data memory and parity data from parity memory, and also configured to produce display, whether error is occurred in data during storage within data memory

Error correction circuit for dynamic RAM system, has read tree to receive data from data memory and parity data from parity memory, and also configured to produce display, whether error is occurred in data during storage within data memory

机译:用于动态RAM系统的纠错电路,具有读取树以接收来自数据存储器的数据和来自奇偶校验存储器的奇偶校验数据,并且还被配置成产生显示,即在数据存储器内存储期间是否在数据中发生错误

摘要

The circuit has a data memory (52) to receive and store a data, and a write tree (56) to receive the data and produce a parity data. A parity memory (54) receives and holds the parity data. A read tree (58) receives the data from the data memory and thee parity data from the parity memory. The read tree also produces a display, whether an error is occurred in the data during storage within the data memory. Independent claims are also included for the following: (1) an application housing with an application chip and a evidently good chip (2) a memory device with a data memory (3) a method for detecting an error in a memory device (4) a method for manufacturing an application housing (5) a error correction method.
机译:该电路具有用于接收和存储数据的数据存储器(52)以及用于接收数据并产生奇偶校验数据的写树(56)。奇偶校验存储器(54)接收并保存奇偶校验数据。读取树(58)从数据存储器接收数据,并从奇偶校验存储器接收奇偶校验数据。读取的树还会显示在数据存储器中存储期间是否在数据中发生错误。还包括以下方面的独立权利要求:(1)具有应用芯片和显然良好的芯片的应用壳体(2)具有数据存储器的存储设备(3)检测存储设备中的错误的方法(4)一种用于制造应用壳体的方法(5),纠错方法。

著录项

  • 公开/公告号DE102006007326A1

    专利类型

  • 公开/公告日2006-08-24

    原文格式PDF

  • 申请/专利权人 INFINEON TECHNOLOGIES AG;

    申请/专利号DE20061007326

  • 发明设计人 BOWYER STEPHEN;DANIEL ALAN;

    申请日2006-02-16

  • 分类号G11C29/52;G06F11/10;G06F11/08;

  • 国家 DE

  • 入库时间 2022-08-21 21:20:08

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