Power amplifier output stage using MOS technology rail-to-rail mirrors

摘要

The output stage has a control stage (5) which comprises a pnp transistor (T1) that clamps a control current (I1) to the upper half-stage output (3) and an npn transistor (T2) which clamps the control current (I2) to the lower half-stage output (4). The bases of the bipolar transistors receive a control voltage (Ve) from an input terminal (E) and the current mirrors have the same ratio. The control stage inputs identical currents to the first MOS transistors (M10,M11) at the nominal control voltage. Resistors (R1,R4) of the same value are inserted between the respective emitters of the second (T2) and seventh (T7) bipolar transistors and the negative loop while resistor (R2,R3) of the same value are inserted between the second (T2) and third (T3) and between the fourth (T4) and fifth (T5) bipolar transistors.