Low-power low-harmonic CMOS clock driver with a prefilter

摘要

Harmonic generation in a CMOS clock driver system is reduced by low-pass filtering the clock signal before applying it to the output transistors 116,118. The output clock signal is of sinusoidal form. The series resistor in the RC filter may comprise the channels of complementary MOS transistors 122,124. A symmetrical output waveform is ensured, despite manufacturing variations, by matching of the output transistors 116,118 with respect to the filtering transistors 122,124. The diode-connected bipolar transistors 117 and 119 reduce the output swing to 1.25 volts given a supply voltage OSC_VCC of 2.75 volts. The clock driver may be used in battery powered devices such as pagers, computers, personal digital assistants and radiotelephones.