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System and method to reduce phase offset and phase jitter in phase-locked and delay-locked loops using self-biased circuits

机译:使用自偏置电路减少锁相环和延迟锁相环中的相位偏移和相位抖动的系统和方法

摘要

A system and method for using self-biased circuits to reduce phase jitter and phase offset in phase locked loops and frequency is disclosed. A self-biased apparatus for aligning a reference signal having reference phase with a feedback signal having a feedback phase includes a phase- frequency detector for comparing the reference phase and the feedback phase. The phase-frequency detector produces a phase-frequency detector output proportional to a difference between the reference phase and the feedback phase. A charge pump, coupled to the phase-frequency detector, outputs a charge pump output in response to the phase-frequency detector output. A loop filter, coupled to the charge pump, filters the charge pump output to produce a control voltage. A bias generator is coupled to the loop filter to generate a bias signal to bias the charge pump, causing the charge pump to generate a bias voltage substantially equivalent to the control voltage. The bias voltage is sufficient to cause the charge pump to output substantially zero current when the reference phase substantially equals the feedback phase. A voltage- controlled element, coupled to the phase-frequency detector and the bias generator, is controlled by the control voltage to modify the feedback signal having the feedback phase such that the feedback phase and the reference phase are substantially aligned. The invention may be implemented as part of a multiple loop apparatus including a first loop to generate a first loop output signal having a frequency that is substantially equal to an integral multiple, N, of the frequency of the input signal and a second loop, coupled to the first loop, to generate a second loop output signal from said first loop output signal, wherein the second loop output signal is substantially in phase with the input signal and has a frequency substantially equal to the integer multiple, N, of the frequency of the input signal.
机译:公开了一种用于使用自偏置电路来减小锁相环和频率中的相位抖动和相位偏移的系统和方法。用于将具有参考相位的参考信号与具有反馈相位的反馈信号对准的自偏置设备包括用于比较参考相位和反馈相位的相频检测器。相频检测器产生与基准相位和反馈相位之差成比例的相频检测器输出。耦合到相频检测器的电荷泵响应于相频检测器输出而输出电荷泵输出。耦合到电荷泵的环路滤波器对电荷泵的输出进行滤波以产生控制电压。偏置发生器耦合到环路滤波器,以生成偏置信号以偏置电荷泵,从而使电荷泵生成基本等于控制电压的偏置电压。当参考相位基本等于反馈相位时,偏置电压足以使电荷泵输出基本为零的电流。耦合至相频检测器和偏置发生器的压控元件由控制电压控制,以修改具有反馈相位的反馈信号,从而使反馈相位和参考相位基本对准。本发明可以被实现为包括第一环路的多环路设备的一部分,该多环路设备产生第一环路输出信号,该第一环路输出信号的频率基本上等于输入信号的频率的整数倍N与耦合的第二环路的频率相同。到第一环路,以从所述第一环路输出信号产生第二环路输出信号,其中第二环路输出信号与输入信号基本上同相,并且具有基本上等于频率的整数倍N的频率。输入信号。

著录项

  • 公开/公告号US5727037A

    专利类型

  • 公开/公告日1998-03-10

    原文格式PDF

  • 申请/专利权人 SILICON GRAPHICS INC.;

    申请/专利号US19960592736

  • 发明设计人 JOHN GEORGE MANEATIS;

    申请日1996-01-26

  • 分类号H03D3/24;

  • 国家 US

  • 入库时间 2022-08-22 02:40:01

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