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Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping

机译:提供地址断点,分支断点和单步执行的方法和装置

摘要

A method and apparatus for providing address breakpoints, branch breakpoints, and single stepping is described. According to one aspect of the invention, a processor is provided which generally includes an execution unit, a first storage area, and an address breakpoint unit. The execution unit recognizes a first debug event in response to the execution of an instruction which causes a branch to be taken. The first storage area has stored therein information. The address breakpoint unit is coupled to the first storage area to receive the information. The address breakpoint unit is also coupled to the execution unit to receive addresses. The address breakpoint unit determines whether the addresses it receives form the execution unit are identified by the information. The execution unit recognizes a second debug event when the address breakpoint unit indicates one of these addresses is identified by the information.
机译:描述了一种用于提供地址断点,分支断点和单步执行的方法和装置。根据本发明的一个方面,提供了一种处理器,该处理器通常包括执行单元,第一存储区域和地址断点单元。执行单元响应于导致分支被采用的指令的执行来识别第一调试事件。第一存储区域已在其中存储信息。地址断点单元耦合到第一存储区域以接收信息。地址断点单元还耦合到执行单元以接收地址。地址断点单元确定该信息是否标识了它从执行单元接收的地址。当地址断点单元指示这些地址之一由信息标识时,执行单元将识别第二调试事件。

著录项

  • 公开/公告号US5740413A

    专利类型

  • 公开/公告日1998-04-14

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US19970899085

  • 发明设计人 GARY HAMMOND;DONALD ALPERT;

    申请日1997-07-23

  • 分类号G06F11/30;

  • 国家 US

  • 入库时间 2022-08-22 02:39:46

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