Error correction decoder that operates in either ARDS system or a RBDS system

摘要

A decoding method and circuit takes into consideration two different techniques of using offset words in error correction coding by subtracting the offset word in a parallel mode from a calculated syndrome. In an error correction decoder (36) an entire incoming data block (26 bits, where 16 are data and 10 are parity) is read into a polynomial divider (11). The invention enables a single data receiver (30) to operate using error correction offset, words A, B, C, and D, in a first radio data system, or the offset words A, B, C, D, and E, in a second radio data system. In accordance with an error correction decoder of this invention the decoder is arranged with a parallel-bit output offset counter (13), an offset word generator (16), and a syndrome storage register (15) coupled to the polynomial divider (11) for enabling the subtracting of an offset word, in parallel, from calculated syndromes.