Automated system and method for identifying critical timing paths in integrated circuit layouts for use with automated circuit layout system

摘要

A computer aided design system converts system level timing constraints to the minimum number of path-based timing constraints necessary to represent the same timing constraints as the system level timing constraints. Using a data structure for each node of the circuit, signal arrival times and required arrival times for each node are generated for each high level timing constraint, and the worst slack time is identified for each node. Then, a node with a worst slack time is selected, the constraint associated with that worst slack time is identified, and then a worst case path from a start node of the identified constraint through the selected node to an end node of the identified constraint is determined. The start and required signal arrival times associated with the identified constraint's start and end nodes in the determined path are also identified. Then the determined path, and the maximum signal traversal time associated with that path are written to a path-based constraint data structure, and all the nodes in the determined path are marked as having been processed. Additional path- based constraints are generated, each time using an unmarked node having a worst remaining slack time, until all nodes in the circuit netlist having identified slack times have been included in at least one path- based constraint. The set of path-based constraints are used by a circuit layout generator to generate a circuit layout that meets the specified timing constraints.