Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin

摘要

Presented is test system for use in debugging functional and electrical failures of an integrated circuit. The test system includes a diagnostics retrieval system and a test access port retrieval system external to the integrated circuit under test, and a debug trigger apparatus and test access port within the integrated circuit under test. The programmable debug trigger apparatus which resides internal and integral to the integrated circuit generates a trigger capture signal within a programmed delay after a set of monitored integrated circuit signals matches a programmed trigger condition. The test access port of the integrated circuit monitors a plurality of test nodes located throughout the integrated circuit and latches a set of test node signals present on test nodes located throughout the integrated circuit when it receives a trigger capture signal from the debug trigger apparatus. The trigger capture signal is also output to an external pin of the integrated circuit as an external pulse signal to indicate that the test access port has been latched and may be downloaded by the test access port retrieval system. The integrated circuit also includes a reset input for resetting the integrated circuit to an initial state. The diagnostics retrieval system is configured to program the programmable debug trigger apparatus in the integrated circuit to set up a trigger condition and to set the programmed delay to a first delay value. The diagnostics retrieval system then initiates operation of the integrated circuit and monitors the external pulse signal. When it receives an external pulse signal, the diagnostics retrieval system causes the test access port retrieval system to download a first set of test node signals from the test access port. The diagnostics retrieval system may then reset the integrated circuit, reprogram the trigger condition, and set the programmed delay to a second delay value which is a known increment greater than the first delay value, and the process is repeated to obtain a second set of downloaded test node signals. The process may be repeated to collect as many trigger event samples as are needed to form a useful trace of test node events for use in debugging functional and electrical failures of the integrated circuit under test.