Method and apparatus for testing analog and digital circuitry within a larger circuit

摘要

A circuit including analog circuitry, digital circuitry partitioned from the analog circuitry, and a boundary scan cell chain along the boundary between the analog and digital circuitry. The chain can be controlled to decouple the analog circuitry from the digital circuitry and supply selected test signals to nodes along the boundary between the analog and digital circuitry during testing. Typically, the circuit is an integrated circuit having external pins for asserting signals directly to and receiving signals directly from each of the analog circuitry, digital circuitry, and boundary scan cell chain. Preferably, each cell of the chain comprises a first multiplexer, a flip- flop, and a second multiplexer having an input coupled to the flip- flop's output, another input coupled to one of the analog circuitry and the digital circuitry, and an output coupled to another of the analog circuitry and the digital circuitry. The cells are serially coupled together so that the chain can be controlled to operate in any of four modes: a non-test mode in which the chain is transparent to the analog and digital circuitry; a serial shift mode in which data values are shifted sequentially into or out of the chain (while the chain is transparent to the analog and digital circuitry); a parallel load mode in which data values are shifted sequentially into the chain and these data values are also sequentially shifted into the analog circuitry and digital circuitry; and a test mode in which data values (previously loaded into the chain) are asserted simultaneously to the analog and digital circuitry. Other embodiments are a boundary scan cell chain of the type used in such a circuit, one of the cells used in such chain, and methods of testing such a circuit.