Single transition per evaluation phase latch circuit for pipelined true- single-phase synchronous logic circuit

摘要

A latch circuit has an enable circuit responds to clock pulse levels of a first polarity by outputting an enabling voltage of a second polarity opposite to the first polarity. The latch circuit also has first and second inverters which each have an output, a first biasing input connected to a first polarity voltage, a first input, a second a biasing input receiving the enabling voltage from the enable circuit and a second input. When enabled by the enabling voltage, each inverter drives its respective output to a voltage of the first polarity in response to receiving a signal of the second polarity at its first input. Alternatively, when enabled, each inverter drives its respective output to a voltage of the second polarity in response to receiving a signal of the first polarity at its second input. The first input of the first inverter receives, between the leading and trailing edges of the first polarity clock pulse levels, a signal to be stored. At other times, the first input of the first inverter receives a signal of the first polarity. The second input of the first inverter is connected to an output of the second inverter. Likewise, the first input of the second inverter receives, between the leading and trailing edges of the clock pulse levels of the first polarity, a complement of the signal to be stored. At other times, the first input of the second inverter receives a signal of the first polarity. The second input of the second inverter is connected to the output of the first inverter. This particular interconnection of second outputs and receipt of signals at the first inputs causes the signals outputted from the first and second inverters to transition from the first polarity to the second polarity no more than once during each clock pulse level of the first polarity.