首页> 外国专利> MICROPROCESSOR PREFETCHING PARALLELLY DATA FOR INSTRUCTION, USING DATA USED MOST LATELY AND EXECUTING INFERENTIALLY INSTRUCTION AND ITS OPERATION METHOD

MICROPROCESSOR PREFETCHING PARALLELLY DATA FOR INSTRUCTION, USING DATA USED MOST LATELY AND EXECUTING INFERENTIALLY INSTRUCTION AND ITS OPERATION METHOD

机译:微处理机对指令的并行数据进行预取,使用最晚使用的数据和推论指令及其操作方法

摘要

PROBLEM TO BE SOLVED: To obtain a method which operates a microprocessor having an accumulation supply source on a chip by prefetching parallelly data for an instruction, using data that are used the most lately and executing inferentially the instruction. ;SOLUTION: A system no includes a microprocessor 12, has a bus B and is connected to various external devices. The microprocessor 12 reads memory hierarchy to an accumulation system and includes a hierarchy on which data are written. The system 10 further includes L2 universal cache 20 and is connected to L1 data cache 18 through a bus 21. The cache 20 includes an access controller 22. The controller 22 receives such requests to access the cache 20, and there, the requests fetch or prefetch information from the cache 20.;COPYRIGHT: (C)1999,JPO
机译:要解决的问题:要获得一种方法,该方法通过使用最近使用的数据并以推断方式执行该指令来并行地预取指令数据,从而操作在芯片上具有累积供应源的微处理器。 ;解决方案:系统No包括微处理器12,具有总线B,并连接到各种外部设备。微处理器12将存储器层次结构读取到累积系统,并且包括在其上写入数据的层次结构。系统10还包括L2通用高速缓存20,并且通过总线21连接到L1数据高速缓存18。高速缓存20包括访问控制器22。控制器22接收这样的请求以访问高速缓存20,并且在那里,请求被获取或访问。从缓存20中预取信息;版权:(C)1999,JPO

著录项

  • 公开/公告号JPH1124924A

    专利类型

  • 公开/公告日1999-01-29

    原文格式PDF

  • 申请/专利权人 TEXAS INSTR INC TI;

    申请/专利号JP19980031915

  • 发明设计人 SHIELL JONATHAN H;CAI GEORGE Z N;

    申请日1998-01-05

  • 分类号G06F9/38;G06F12/08;

  • 国家 JP

  • 入库时间 2022-08-22 02:33:52

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