STRESS TEST METHOD FOR INTEGRATED CIRCUIT WITH MEMORY AND INTEGRATED CIRCUIT WITH STRESS TESTER FOR MEMORY

摘要

PROBLEM TO BE SOLVED: To shorten the time required for testing a memory by forming a stress select means on a substrate and performing a stress test only at a selected part on a memory block in order to decide whether the memory block is accepted or not. ;SOLUTION: An integrated circuit 10 having enhanced test capacity comprises a substrate 11, and a memory block 20 including a plurality of memory cells 25 arranged in a matrix having a plurality of rows R and columns C. A selectable stress tester 30 including a selectable test pattern generating means is formed on the substrate 11. The test pattern generating means generates a test pattern selectively over the boundary only between two adjacent rows R and two adjacent columns C of the memory block 20. A decision is made whether a selected part of the memory block 20 is acceptable or not by applying a high frequency waveform signal of about 100 MHz.;COPYRIGHT: (C)1999,JPO