PURPOSE: To provide a debugging device which is suited to a CPU of such a type that interrupts the execution of a program by preventing the transmission of a signal that instructs the interruption of execution of the program to the CPU from an address trap circuit until one of component instructions of the program is carried out. ;CONSTITUTION: An interruption request signal IREQ1 sent to a CPU 30 from an address trap circuit 10 is temporarily inputted to an interruption instruction control circuit 20. The circuit 20 prevents the transmission of the signal IREQ1 to the CPU 30. Then the memory read signal MEMRD and the debug routine under-execution signal DIACK sent from the CPU 30 are inputted to the circuit 20. Based on these signals, the signal IREQ1 is converted into an interruption signal IREQ2 which is sent to the CPU 30. Thus a debugging device of such a constitution is suitable to the CPU 30 of such a type that interrupts the execution of a program.;COPYRIGHT: (C)1995,JPO
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