High current CMOS charge pump, particularly for flash EEPROM memories

摘要

A voltage multiplier circuit for integrated circuits, comprising two mirrored sections driven by control signals (PH00, PH01, PH0_P; PH10, PH11, PH1_P) generated by a logic circuitry which receives, as input signals, an enable signal (en) and a clock signal (clk), wherein each mirrored section includes N stages and each stage comprises a capacitor (C00, C01, C02; C10, C11, C12) having a lower terminal and an upper terminal, the lower terminal is connected to a first switch (INV0, NCH00, NCH01; INV1, NCH10, NCH11) that, in closed condition, couples the lower terminal of the capacitor to ground (GND), said lower terminal of the capacitor being additionally connected to a second switch (INV0, PCH00, PCH01; INV1, PCH10, PCH11) that, in closed condition, couples the lower terminal of the capacitor to the supply voltage (Vpp), as far as the first stage is concerned, or to the upper terminal of the capacitor of the previous stage, the upper terminal of the capacitor is connected to a third switch (NCH02, NCH03, NCH04; NCH12, NCH13, NCH14) that, in closed condition, couples the upper terminal of the capacitor to the supply voltage (Vpp), the upper terminal of the capacitor (CO1; C11) of the last-but-one stage is connected to a last two-terminal switch (NCH08;NCH18) that, in closed in condition, couples the upper terminal of the capacitor of the last-but-one stage to the output of the voltage multiplier; said control signals directly or indirectly drive said switches such that, when the voltage multiplier is enabled (en = 1), at a rate determined by said clock signal (clk), each mirrored section in alternating times is switched over from a charging phase to a discharging phase, so that while a mirrored section is in charging phase, the other one is in discharging phase and vice versa; when a mirrored section of the circuit is charging phase, the last switch (NCH08; NCH18) and all second switches thereof (INV0, PCH00, PCH01; INV1, NCH10, NCH11) are in open condition, while its first switches (INV0, NCH00, NCH01; INV1, NCH10, NCH11) and its third switches (NCH02, NCH03, NCH04; NCH12, NCH13, NCH14) are in closed condition, so that all capacitors of this circuit section are parallel connected between the power supply voltage (Vpp) and ground (GND) and are charged up to said supply voltage (Vpp); when a mirrored section of the circuit is in discharging phase, all its first switches (INV0, PCH00, PCH01; INV1, NCH10, NCH11) and third switches (NCH02, NCH03, NCH04; NCH12, NCH13, NCH14) are in open condition, while its last switch (NCH08; NCH18) and all its second switches (INV0, PCH00, PCH01; INV1, PCH10, PCH11) are in closed condition, so that all capacitors are serially connected with one another, the lower terminal of the capacitor (C00; C10) of the first stage being connected to the supply voltage (Vpp) and the upper terminal of the capacitor of the last-but-one stage being connected to the output of the voltage multiplier; when the voltage multiplier is disabled (en = 0), both mirrored sections of the circuit are in charging phase.