Interconnection track connecting by several levels of metal an isolated gate of a transistor to a discharge diode inside an integrated circuit and method of manufacturing such a track

摘要

The multiple level interconnection track connects an isolating grid (GR) to a discharge diode (DD). The track configuration has a first layer of track extending under the highest level metallisation level. The highest point (M2) is connected to the grid and has a length (L1) above a critical length. A second length (L2) is selected in the first track, having a length below the critical length. A space is formed between two isolating layers (IS1,IS2) on the same metallisation level (M1) then filled with metallic deposition (CT1) forming contact between the two lower sections of track (BP1,BP2) forming a track following the initial geometric configuration.