A timing signal generation signal, a semiconductor integrated circuit device, a semiconductor integrated circuit system to which a timing signal generation circuit is applied, and a signal transmission system

摘要

The present invention provides a semiconductor integrated circuit device having a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying a control command activated for a predetermined period as a control signal to the DRAM core . The timing adjustment circuit generates n different clocks whose phases are varied relative to the supplied reference clock, and the second predetermined clock of the second clock among the n clocks from the first predetermined clock pulse of the first clock among the n clocks And activates a control command during a predetermined operation cycle only for a period up to the pulse to generate a DRAM control signal. Thus, it is possible to perform timing adjustment with a relatively high accuracy in a short time.