The present invention allows the input / output device having the highest priority to temporarily change priority in the course of the transfer with the memory so that the input / output device having the next priority can perform the transfer operation so as to change the priority programmatically A plurality of input / output devices connected to a plurality of input / output devices; a plurality of input / output devices connected to the plurality of input / output devices; A control logic unit for performing an interface between the CPU, the input / output device and the memory, and a control unit for storing a transfer value for each input / output device 1 register section, a second register section for storing the maximum allowable transfer value, A comparator for comparing a value of the second register with a current transfer value currently in progress, and a comparator for comparing the value of the first register with the value of the current register, And a third register unit for temporarily storing the transfer value stored in the temporary register unit when the value is greater than the maximum allowable transfer value.
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