SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH BUILT-IN TEST CIRCUIT FOR APPLYING STRESS TO TIMING GENERATOR IN BURN-IN TEST

摘要

The semiconductor memory device has a device identification code (ID1) to determine whether the packet signal (RQ) address, the timing generator 16 has identified an input device coupled to the stored apparatus identification code (ID1) and a packet signal code ( ID2) receiving signals between the between the correspondence for a response to the heat signal (IDHIT) indicating to start the control sequence for the data access, tested here represent a command for a burn-in test signal (TP) and a packet signal (RQ) circuit ( to 12) to the share, and a logic gate (23) for generating a heat signal (IDHIT) directly installed from the inside of the mode signal (tEST) indicates the test mode, the stored unit identification code (ID1) and the test signal (TP) a timing generator (16) regardless of correspondence begins the control sequence in the burn-in test.