SEMICONDUCTOR MEMORY WITH INVERTED WRITE-BACK CAPABILITY AND METHOD OF TESTING A MEMORY USING INVERTED WRITE-BACK

摘要

The present invention relates to an integrated circuit having a memory with improved test effect and a method of operating the same. The memory includes SRAM cells that are powered up in good condition, and the good state is less susceptible to noise and other unwanted effects that can draw less standby power and cause corruption of the stored data state. The memory test method is a maintenance of a good data state. A memory cell contains a high current state. When a standby current is measured after recording a maintenance of a good data state, the worst-case standby current is measured. This test method also includes a disturbance test, in which the worst case test is performed because the cell under test or neighboring cells in adjacent rows is repeatedly accessed and the good condition is more stable than its repair. Since a circuit for performing inverted recording of the stored contents is also described, such recording can be executed without requiring a read and write operation from an external terminal of the circuit.