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Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access
Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access
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机译:双总线网络高速缓存控制器系统,具有快速的无效周期和减少的高速缓存访问延迟
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摘要
A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.
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