Super-compact hardware architecture for IDCT computation

摘要

An Inverse Discrete Cosine Transform processor employs symmetry and reusable elements to use a fewer number of gates while maintaining processing speed at an acceptable level. Even and odd sums are generated simultaneously by even and odd sum generators. A butterfly operation is then performed on the on the even and odd sums to produce pairs of transformed elements simultaneously. For an 8×8 block, the even and odd sum generators can be designed to a generate four pairs of even and odd sums sequentially. This design allows a single row or column of eight elements to be processed in 4 clock cycles. A horizontal transformation on all eight rows of the block can be performed in 32 cycles. A vertical transformation can then be performed by storing the transformed rows in a second memory, reading out columns from the second memory, and using the same hardware to generate the sums and perform the butterfly operation on the columns. An entire two-dimensional transformation can be performed in only 64 clock cycles.