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Hardware design implementation of HEVC IDCT algorithm with high-level synthesis

机译：具有高级综合的HEVC IDCT算法的硬件设计实现

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Μαγουλιανίτης Βασίλειος;
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年度 2015
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正文语种 en
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专利

1. Hardware solution for implementing the entire inverse IDCTs in HEVC decoder [J] . Nayeri Hamid Reza, Zargari Farzad International journal of electronics . 2018 ,第7a9期

机译：在HEVC解码器中实现整个逆IDCT的硬件解决方案
2. An FPGA comparative study of high-level and low-level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules [J] . Ben Atitallah Ahmed, Kammoun Manel, Ali Karim M. A., International journal of circuit theory and applications . 2020 ,第8期

机译：HEVC内部，逆量化和IDCT / IDST 2D模块的高级和低级组合设计的FPGA比较研究
3. Hardware Implementation of IDCT Fast Algorithms for Still Images Decompression in the Jpeg Standard [J] . Sebastian Koryciak, Agnieszka D?browska-Boruch, Kazimierz Wiatr Image Processing & Communications . 2013 ,第4期

机译：Jpeg标准中用于静止图像解压缩的IDCT快速算法的硬件实现
4. High-level synthesis hardware implementation and verification of HEVC DCT on SoC-FPGA [C] . Belal Mohamed, Amr Elsayed, Omar Amin, International Computer Engineering Conference . 2017

机译：SoC-FPGA上HEVC DCT的高级综合硬件实现和验证
5. Algorithms and Hardware Co-design of HEVC Intra Encoders [D] . Zhang, Yuanzhi. 2019

机译：HEVC intra编码器的算法和硬件共同设计
6. A Novel Hardware–Software Co-Design and Implementation of the HOG Algorithm [O] . Sina Ghaffari, Parastoo Soleimani, Kin Fun Li, 2020

机译：一种新颖的硬件 - 软件协同设计和实现的猪算法
7. FPGA implementation of HEVC intra prediction using high-level synthesis [O] . Kalalı Ercan, Kalali Ercan, Hamzaoğlu İlker, 2016

机译：使用高级综合的HEVC帧内预测的FPGA实现

Hardware design implementation of HEVC IDCT algorithm with high-level synthesis

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