Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool

摘要

A method and apparatus for identifying gated clocks within a circuit design. In a typical design, each of the number of gated clock signals is uniquely determined by a particular logical combination of a number of raw clock signals and a number of enable signals. In the present invention, the gated clock signals may be identified by: identifying which of the number of raw clock signals is coupled, through combinational logic, to a selected one of the number of state devices, thereby resulting in an identified raw clock signal; identifying which of the number of enable signals is coupled, through combinational logic, to the selected one of the number of state devices, thereby resulting in an identified enable signal; and determining which of the number of gated clock signals is uniquely determined by the particular combination of the identified raw clock signal and the identified enable signal.