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DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT
DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT
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机译:降低时钟门控同步电路和时钟门控同步电路内功率消耗的设计结构
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摘要
A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.
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