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Method for generating an improved model for evaluating the operation of an integrated circuit design
Method for generating an improved model for evaluating the operation of an integrated circuit design
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机译:生成用于评估集成电路设计的操作的改进模型的方法
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摘要
Modeling of propagation delay and output transition time by use of fitting functions comprised of standard Taylor series and inverse powers is disclosed. These components are used as a basis for generating an equation that predicts circuit performance over a wide range of input transition and output capacitive loads. The present invention includes a computer implemented method for adding functions to the fitting functions or removing functions from the fitting functions until an acceptable error limit has been reached.
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