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Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram
Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram
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机译:具有一体式sram的dram,包括多组地址锁存器,每组地址锁存器与多个sram中的一个相关联
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摘要
A memory 601 comprising a plurality of static random access cell arrays 701, and a plurality of sets of latches 703 each for storing address bits associated with data stored in a corresponding one of the static random access cell arrays 701. Bit comparison circuitry 503 compares a received address bit with an address bit stored in each of the plurality of sets of latches 703 and enables access to a selected one of the static random cell arrays 701 corresponding to the set of latches 703 storing an address bit matching the received bit.
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