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Bond pad functional layout on die to improve package manufacturability and assembly

机译:芯片上的焊盘功能布局,以提高封装的可制造性和组装性

摘要

An integrated circuit package which has a staggered bond wire pattern that increases the bond finger width to pad pitch ratio of the package. The package includes a first bond shelf, a second bond shelf and a third bond shelf. Mounted to the package is an integrated circuit which has a plurality of die pads. The die pads are arranged in a pattern of groups, wherein each group has a first die pad that is adjacent to a second die pad, and a third die pad that is adjacent to the second die pad and a first die pad of an adjacent group. Bond wires connect the first die pads to the first bond shelf, the second die pads to the second bond shelf and the third die pads to the third bond shelf, so that each adjacent die pad is connected to a different bond shelf. The staggered bond pattern maximizes the bond finger width of the package.
机译:一种具有交错键合线图案的集成电路封装,其增加了键合指的宽度与封装的焊盘间距之比。该包装包括第一结合架,第二结合架和第三结合架。安装到封装的是具有多个管芯焊盘的集成电路。管芯焊盘以组的形式布置,其中每个组具有与第二管芯焊盘相邻的第一管芯焊盘以及与第二管芯焊盘相邻的第三管芯焊盘和相邻组的第一管芯焊盘。键合线将第一管芯焊盘连接到第一键合架,将第二管芯焊盘连接到第二键合架,将第三管芯焊盘连接到第三键合架,使得每个相邻的管芯焊盘都连接到不同的键合架。交错的接合图案可最大化包装的接合指宽度。

著录项

  • 公开/公告号US5895977A

    专利类型

  • 公开/公告日1999-04-20

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US19960694929

  • 发明设计人 KOUSHIK BANERJEE;

    申请日1996-08-08

  • 分类号H01L23/48;H01L23/02;

  • 国家 US

  • 入库时间 2022-08-22 02:08:16

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