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Variable delaying circuit having a nearly linear delay characteristic
Variable delaying circuit having a nearly linear delay characteristic
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机译:具有几乎线性延迟特性的可变延迟电路
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摘要
A first capacitor 7, a resistor 5, and a second capacitor 6 are connected in series between an output node A and a first power supply line 22. In addition, a first switch 8 is connected between the connected point of the first capacitor 7 and the resistor 5 and a second power supply line. A second switch 9 is connected in parallel with the second capacitor 6. The first and second switches 8 and 9 are opened or closed corresponding to the level of the input signal.
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