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Variable delay circuit for delaying logic signals, characterized by a delay time that is a linear function of a control voltage
Variable delay circuit for delaying logic signals, characterized by a delay time that is a linear function of a control voltage
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机译:用于延迟逻辑信号的可变延迟电路,其特征在于延迟时间是控制电压的线性函数
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摘要
A delay circuit for delaying high-speed logic signals has a continuously-variable delay which is a linear function of a control current. The resulting delay time may be set as short as a single logic gate delay. The CMOS delay circuit comprises delay means having as its output an internal signal characterized by an internal signal swing, coupled to amplifier means whose output is the delayed logic signal, characterized by a settling time. The amplifier means contributes minimal delay. The swing of the internal signal of the delay circuit is controlled by differential negative feedback to be just sufficient to drive the next stage, while the delay circuit's settling time is controlled by capacitively coupled positive feedback to be as short as the delay itself. The differential negative feedback is provided by four MOS devices.
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