首页>
外国专利>
Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines
Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines
A method and structure are described for making DRAM devices having bit line contacts for memory cells and landing plugs for peripheral devices with a Ti/TiN barrier layer patterned to form bit lines and local interconnections. FETs are formed on the substrate for memory cells and for devices in the peripheral area. A planar first insulating layer is deposited, and contact openings are formed to the devices. A Ti/TiN barrier layer is deposited in the contact openings and a tungsten (W) layer is deposited and selectively etched back to the barrier layer. The barrier layer is then patterned to form bit lines and local interconnections. A second insulating layer is deposited, and capacitor node contact openings are etched and filled with polysilicon to form node contacts on which capacitors are fabricated. A planar third insulating layer is formed and multilevel contact openings are etched to landing plugs. Metal plugs are formed in the multilevel contact openings, and a first metal is deposited and patterned to form the first level of metal interconnections. The reduced height of the Ti/TiN bit lines and the landing plug contacts significantly reduce the aspect ratio of the multilevel contacts, allowing for fabricating DRAM circuits with higher density and improved reliability.
展开▼
机译:描述了一种方法和结构,该方法和结构用于制造具有用于存储单元的位线触点和用于外围设备的着陆栓的DRAM设备,其中Ti / TiN势垒层被构图以形成位线和局部互连。在存储单元和外围区域中的器件的衬底上形成FET。沉积平面的第一绝缘层,并且形成到器件的接触开口。在接触开口中沉积Ti / TiN阻挡层,并沉积钨(W)层并选择性地回蚀到阻挡层。然后对阻挡层进行构图以形成位线和局部互连。沉积第二绝缘层,并且蚀刻电容器节点接触开口并用多晶硅填充以形成在其上制造电容器的节点接触。形成平面的第三绝缘层,并且将多级接触开口蚀刻到接地插塞。在多级接触开口中形成金属塞,并且沉积第一金属并对其构图以形成第一级金属互连。 Ti / TiN位线和着陆插头触点的高度降低,大大降低了多级触点的纵横比,从而可以制造出密度更高,可靠性更高的DRAM电路。
展开▼