Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts

摘要

DRAM devices are made having self-aligned tungsten landing plug contacts to gate electrodes for capacitor-under-bit line (CUB) for reduced aspect ratio contact openings. A planar insulating layer is formed, and openings for bit line contacts, node contacts, and contacts on the chip periphery are concurrently etched for metal landing plugs. A TiN/Ti/N.sup.+ polysilicon multilayer is deposited and annealed to form low contact resistance to the substrate A tungsten (W) layer is then deposited and etched back to form W landing plug contacts in the contact openings, which reduce the aspect ratio for the multilevel contacts. A Si. sub.3 N.sub.4 etch-stop layer and a BPSG are deposited and planarized. Capacitor openings are etched in the BPSG aligned over the node contacts. A conformal conducting layer and a planarized polymer are deposited and polished back to complete the bottom electrodes in the capacitor openings. After removing the polymer, an interelectrode dielectric layer and a conformal conducting layer (top electrode) are deposited and patterned to complete the capacitors. A planar insulating layer is formed and the interlevel contact openings etched with reduced aspect ratios to the landing plugs. W/TiN plugs are formed in the openings, and a first level of metal interconnections is formed.