ECL to CMOS level translator using delayed feedback for high speed BICMOS applications

摘要

A voltage level translator for converting a small-signal differential ECL input signal into a full rail, single-ended CMOS output signal, wherein the difference in current generated by a pair of P- channel transistors as a result in a transitioning of the ECL signal is "mirrored" by a pair of N-channel output transistors, causing the CMOS output voltage to transition, the delay in transitioning of the output transistors being minimized through the use of delayed feedback.