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Integrated circuit design system with shared hardware accelerator and processes of designing integrated circuits

机译:具有共享硬件加速器的集成电路设计系统和集成电路设计过程

摘要

An interactive environment is provided for integrated circuit (IC) designers to do an emulation session on a hardware accelerator 111 and then move to simulator 131, and vice versa. An aspect of the present inventive solution swaps memory state and logic storage node state (such as flip-flops and latches) between the accelerator 111 and simulator 131. A complete context switch is performed to create a time shared environment on hardware accelerator 111 so that multiple IC designers can access and use the accelerator. Multiple memory pages can be incorporated to minimize state swap time. Multiple accelerators 111 can be interconnected with a plurality of simulators 131 and a plurality of workstations 101 to allow multiple designers to do interactive operations and allows shifting back and forth between hardware emulation and software simulation.
机译:提供了一种交互式环境,供集成电路(IC)设计人员在硬件加速器111上进行仿真会话,然后移至模拟器131,反之亦然。本发明解决方案的一方面在加速器111和模拟器131之间交换存储器状态和逻辑存储节点状态(例如触发器和锁存器)。执行完整的上下文切换以在硬件加速器111上创建时间共享环境,从而多个IC设计人员可以访问和使用加速器。可以合并多个内存页面以最小化状态交换时间。多个加速器111可以与多个模拟器131和多个工作站101互连,以允许多个设计者进行交互操作,并允许在硬件仿真和软件仿真之间来回切换。

著录项

  • 公开/公告号US5937179A

    专利类型

  • 公开/公告日1999-08-10

    原文格式PDF

  • 申请/专利权人 TEXAS INSTRUMENTS INCORPORATED;

    申请/专利号US19960762172

  • 发明设计人 GARY L. SWOBODA;

    申请日1996-12-09

  • 分类号G06F17/50;G06F9/455;

  • 国家 US

  • 入库时间 2022-08-22 02:07:33

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