Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device

摘要

A computer system is provided including a CPU, a graphics controller, system memory, data steering logic, a DMA controller and arbitration logic. The graphics controller and system memory are coupled to a high- speed data bus. Data accessed by the CPU, the DMA controller and the graphics controller is all stored in the system memory. The data steering logic is also coupled to the high-speed data bus and to a low- speed data bus, and to the CPU. The data steering logic is configured to selectively couple the CPU to either the high-speed data bus or the low- speed data bus, thereby accommodating data transfers between the CPU and a bus device connected to the slow-speed data bus concurrent with data transfers between the graphics controller and the system memory. The data steering logic may also accommodate data transfers by the DMA controller on the slow-speed data bus concurrent with graphics controller data transfers. The arbitration logic arbitrates for access to the system memory between the CPU, DMA controller and graphics controller. In an alternative mode, the data steering logic accommodates data transfers between the CPU and the system memory over both the high- speed and slow- speed buses as a single double width high speed bus. The CPU, graphics controller, DMA controller, data steering logic and arbitration logic as described above may all be included within a single integrated circuit device along with various PC compatibility cores, thus achieving a low- cost, low-space system without sacrificing overall performance.