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Computer system to control the data transfer between a memory and a peripheral device connected to a CPU via a bus
Computer system to control the data transfer between a memory and a peripheral device connected to a CPU via a bus
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机译:用于控制存储器和通过总线连接到CPU的外围设备之间的数据传输的计算机系统
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摘要
In a computer system that includes a memory, a peripheral device to which an address overlapping with a part of an address space assigned to the memory is assigned, a CPU for sending a signal responding an address of an access destination to a bus when the CPU accesses either the memory or the peripheral device, and a bus for connecting the CPU and the peripheral device, a switch for switching a connection and a disconnection between the CPU and the memory via the bus, and an interface portion for receiving a signal sent to the bus from the CPU and specifying an address indicated by the signal and a decoding portion for turning OFF the switch when the address specified by the interface portion is the address assigned to its own device is provided to the peripheral device.
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